Austrochip 2014

22nd Austrian Workshop on Microelectronics
09 October 2014, Graz, Austria.

Graz University of Technology
Institute for Applied Information Processing and Communications

Invited Speakers

Prof. Hubert Kaeslin
"Design and Test of Microchips at Universities, Extravagance or Necessity?"
"Entwurf hochintegrierter Schaltungen an Hochschulen, Extravaganz oder Notwendigkeit?"

Hubert Kaeslin and Michael Schaffner

Probably the best way of preparing for an engineering career in the microelectronics industry is to complete a design project where circuits are not just being modeled and simulated on a computer, but actually fabricated and tested. Master and Ph.D. students at ETH Zürich are indeed given this opportunity. The “How?” and “What does it take?” will be explained. As an example, we will present an ASIC from our on-going research into 3D video processing architectures. Image Domain Warping is a key technology that can be leveraged both for fitting a video stream to displays of different aspect ratios (Aspect Ratio Retargeting) and for producing multiple views on a scenery from a variety of angles for presentation on a multiview auto-stereoscopic display (Multiview Rendering). With a complexity of 6.8 MGE and fabricated in 65 nm CMOS, our ASIC delivers eight views at 28 frames/s and dissipates 550 mW. We believe the opportunity to design and test VLSI circuits prepares our graduates for an engineering career in the best possible way and renders our lab attractive as a research partner.

About the Speaker:
Hubert Kaeslin received both the M.Sc. and the Ph.D. degree in electrical engineering from ETH Zurich, Switzerland, in 1978 and 1985 respectively. Since 1989 he has been heading the Microelectronics Design Center of ETH Zurich which taped out roughly 400 circuit designs under his supervision over the past 25 years, both for research and educational purposes. These activities have led to the publication of a textbook entitled "Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication". His professional interests include dedicated VLSI architectures, energy-efficient circuits, hardware description languages, synchronous and self-timed (GALS) clocking methodologies, electronic design automation, CMOS technology, digital signal processing, IT security, graph theory, and visual formalisms.

Dr. Kaeslin has authored or co-authored more than 75 papers in reviewed journals and conference proceedings. He is Senior Member IEEE and has been awarded the title of professor by ETH in 2010.